IBM unveils chip technology with nearly 100 billion transistors

Rather than pursuing further lateral miniaturization, IBM's approach — which it calls a nanostack architecture — arranges transistors across two stacked layers. Transistor density with the new design comes in at roughly twice what IBM achieved with its 2021 two-nanometer chip, the company said. According to IBM, processors using the nanostack design could achieve performance gains of as much as 50 percent or energy savings of as much as 70 percent relative to the 2021 chip.

To build the structure, IBM starts with two silicon wafers, each carrying nanosheet-style transistors, and fuses them so that one sits inverted atop the other — producing a three-dimensional arrangement that collapses two transistor types into a single compact footprint, the company said. Because the transistors in the upper layer are offset rather than aligned directly above those below, the design reduces wiring complexity and opens the door to using different materials in each layer to tune their performance separately, the company said. IBM also reported a 40 percent improvement in SRAM scaling with the new design.

"It's not just an incremental step," Jay Gambetta, director of IBM Research, said during a press conference, according to MIT Technology Review. "It's a meaningful leap forward."

IBM said it sees a path to production within the next five years. The company does not manufacture chips itself but develops the underlying technology and licenses it to manufacturers. IBM vice president of global semiconductor R&D Huiming Bu declined to name potential partners at a press briefing, according to The New York Times, though the company's past licensees have included Samsung Electronics and Japanese chipmaker Rapidus.

Industry analysts received the announcement positively. "This is a big deal," Dan Hutcheson said, an analyst at TechInsights. "It basically puts another 10 or 15 years on the road map."

Several other organizations are working along similar lines, with Intel $INTC, Samsung, TSMC $TSM, and Belgium's Imec all exploring their own versions of stacked transistor technology. What sets IBM's version apart, the company argues, is the offset positioning of the upper-layer transistors — an arrangement it credits with reducing interconnect complexity in ways that direct-stack designs do not achieve.

IBM said the nanostack technology was developed at its semiconductor research facility in Albany, New York, in collaboration with partners including Lam Research $LRCX, Tokyo Electron, and SCREEN Semiconductor Solutions.